1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method of the same, and particularly to a semiconductor device which includes at least a specific circuit portion having a predetermined function and a spare redundant circuit portion having the same function as the specific circuit portion as well as a connection which can be fused and removed for substituting the redundant circuit portion for a defective specific circuit portion, and a manufacturing method of the same.
2. Description of the Background Art
Generally, semiconductor devices such as static random access memories (SRAMs) and dynamic random access memories (DRAMs) incorporate redundant circuits so as to improve a manufacturing yield of the semiconductor devices. These redundant circuits are employed for preventing reduction of the yield of the semiconductor devices, which may be caused by random defects produced during manufacturing processes of the semiconductor devices. Redundancy is provided with respect to the specific circuit portion having a predetermined function, so that a few possible defects will not impair the function of the semiconductor device as a whole, owing to the redundant circuit portion formed to have the same function as the specific circuit portion. In order to replace the defective specific circuit portion with the redundant circuit portion, there is formed a connection which can be fused, i.e. melted, and removed by a laser beam spot. The type of this redundant circuit is called an open loop formation type.
A constitution of the semiconductor device having redundant element structures of the open loop formation type described above will be schematically described. FIG. 5 is a top view illustrating a wafer in which semiconductor devices generally having the redundant circuits are formed as individual chips. FIG. 6 is a schematic view illustrating internal structures of the semiconductor device having the redundant circuit for each chip.
Referring to FIG. 5, the wafer 1000 includes a plurality of chips (semiconductor devices) 100. Referring to FIG. 6, each chip 100 includes blocks N1, N2, . . . , Nm which have the same function, each including, for example, a plurality of memory cells having the same function in the semiconductor memory device. In order to activate these blocks N1, N2, . . . , Nm, there are formed fuses (links L1, L2, . . . , Lm) which can be blown. In order to replace any of the inactivated blocks N1, N2, . . . , Nm, there is formed a redundant block S having the same function. The fuse (link) Ls can be blown for activating the redundant block S. A field effect transistor 106 serves as a switch for activating the redundant block S. For the execution of the switching function of this field effect transistor 106, there are provided a power supply 103, a resistor 104 and a ground power source 105. In order to detect possible defects in the respective blocks N1, N2, . . . , Nm, there are formed testing pad electrodes 101 and 102 in a pad portion P.
The functional test of the semiconductor device constructed as described above will now be described. Generally, a predetermined circuit test is effected on the semiconductor device after integrated circuits are formed on a substrate such as a wafer through several steps. The wafer 1000 incorporating the chips 100 are processed for detecting the defect in accordance with following procedures. These processing procedures are generally called as a defective circuit repairing step. As executing means for it, there have be known a method in which processing is effected by flowing a predetermined electric signal and a method in which the processing is effected, using a laser beam spot together with an electric signal. Description herein will be made with respect to the latter case in which the processing is effected with the laser beam spot, i.e., a so-called laser trimming (will be also call as "LT" hereinafter) process.
This LT process is effected on the semi-finished wafer 1000, in which the chips have been formed. Specifically, the electric signal for the functional test is first applied to each chip 100 on the wafer 1000 through a testing pad electrode 101 in the pad portion P from a functional test device (not shown; will be called also as "tester"). If the chip 100 is non-defective, an expected signal corresponding to the applied electric signal is output from the testing pad electrode 102. In this operation, the tester determines whether the chip 100 to be processed is defective or not based on a correlation between the electric signal applied to the chip 100 and the output electric signal. If any of the blocks N1, N2, . . . , Nm is determined to be defective, the defective block will be replaced with the redundant block S so that the chip 100 will have the intended function to be achieved. Thus, the chip 100 determined to be defective can have a possibility to become non-defective owing to the existence of the redundant block S.
The replacement of the defective block with the redundant block is performed as follows. A potential at the ground power supply 105 is applied to a gate electrode of the field effect transistor 106, whereby the field effect transistor 106 is maintained to be non-conductive. Thereby, the redundant block S is electrically isolated in the chip 100. The LT process is executed in this condition. As a result thereof, if the block, e.g., N1 in chip 100 is determined to be defective, this defective block N1 is replaced with the redundant block S in the following manner.
In this case, upon detection of the defect in the block N1 by the tester, information relating to the fuses L1 and Ls in the chip 100, in other words, a defective address or position coordinate in the chip and others (i.e., replacement information) are first applied to the LT processing device. This LT processing device operates on the basis of the replacement information to fuse and remove the fuses L1 and Ls by irradiation of the laser beam. By fusing the fuse L1, the defective block N1 is isolated in the chip 100. By fusing the fuse Ls, the voltage of the power supply 103 is applied through the resistor 104 to the gate electrode of the field effect transistor 106. This makes the field effect transistor 106 conductive. Thus, the defective block N1 is replaced with the redundant block S.
Description will be made with respect to an example in which the semiconductor device having the above redundant circuit is a DRAM, and particularly to a case in which blocks having the predetermined functions are memory cell arrays. FIG. 7 is a schematic diagram illustrating structures of a memory cell array in a conventional DRAM. Referring to FIG. 7, the memory cell array 50 is provided with a plurality of word lines WL extending in a row direction and a plurality of bit lines BL extending in a column direction and crossing the word lines WL. A memory cell MC is arranged at an intersection between each word line WL and each bit line BL. A plurality of row decoders 51 are provided corresponding to the word lines WL, respectively. Each row decoder 51 is connected through a word driver 52 to the corresponding word line WL. A plurality of column decoders 53 are provided corresponding to the bit lines BL, respectively.
A spare word line SWL is disposed outside the word lines WL. A spare memory cell SMC is arranged at an intersection between the spare word line SWL and each bit line BL. A spare decoder 54 is provided corresponding to the spare word line SWL. The spare decoder 54 is connected through a spare word driver 55 to the spare word line SWL. These spare word lines SWL, spare decoder 54 and spare word driver 55 form the so-called redundant circuit.
Now, the function of the redundant circuit in the DRAM will be described. The redundant circuit is incorporated in the DRAM for improving the yield of the memory cells in the DRAM. Referring to FIG. 8, description will be given with respect to a memory circuit characteristic test of the DRAM and a defective circuit repairing method using the redundant circuit. First, an operational test is effected on the DRAM with the tester device or others to detect a defective bit MC1 in the memory cell array 50. Then, a fuse FU1 of a word line WL1 including this defective bit MC1 is blown to isolate the defective word line WL1 from the circuit. Then, fuses SFU connected to the spare line SWL of the redundant circuit are selectively blown in a certain combination to form the circuit in such a manner that the spare line SWL will operate only when a signal selecting the defective bit MC1 is entered as an address signal from the exterior. In this manner, by connecting the spare line included in the redundant circuit to the primary line, the DRAM having the defect can be repaired to the non-defective DRAM. The fuses FU1 and SFU are blown by the LT process described before.
Then, the LT process will be specifically described. FIGS. 9A-9C are cross sections of the semiconductor device for illustrating, in this order, the steps in the LT process. Referring to FIG. 9A, the silicon substrate 1 is covered with an interlayer insulating film 2 formed of an oxide film. A polysilicon layer (LT fuse) 3 to which the above LT process is applied is embedded in this interlayer insulating film 2. Interconnection layers 4 formed of aluminum or the like are formed on the interlayer insulating film 2 at a final manufacturing step of the semiconductor device. The polysilicon layer 3 is located at a region between the interconnection layers 4. Apart from the interconnection layers 4, there is formed on the interlayer insulating film 2 a testing pad electrode 5 to be used in the above functional test. This testing pad electrode 5 is formed of aluminum. The polysilicon layer 3 which can be fused and removed is located at a depth t1 of 1 .mu.m or more from the surface of the interlayer insulating film 2. The left-hand area in the figure is illustrated as the link portion L which is a region for forming the LT fuse, and the right-hand portion is illustrated as the pad portion P which is a region for forming the electrode used in the functional test.
Referring to FIG. 9B, an electrode terminal of the tester is pressed onto the surface of the testing pad electrode 5 for detecting the possible defect in the circuit. If the defective portion in the circuit is detected, in accordance with a predetermined logic, the laser beam spot 12 is irradiated to the LT fuse 3 provided in the redundant circuit. This laser beam spot 12 irradiates that region of the interlayer insulating film 2 in which the polysilicon layer 3, i.e., LT fuse is embedded. The laser beam spot 12 irradiated toward the polysilicon layer 3 passes through the interlayer insulating film 2 to the polysilicon layer 3. Thereby, the polysilicon layer 3 absorbs the heat caused by the laser irradiation, and it melts. In this operation, rapid increase of the temperature is caused particularly in the upper portion of the polysilicon layer 3 so that the pressure increases, and thereby the interlayer insulating film 2 over the polysilicon layer 3 is blown off. This reduces the pressure nearly to an atmospheric pressure, and simultaneously, the melted polysilicon layer 3 vaporizes, so that the LT fuse can be blown. This condition is illustrated in FIG. 9C. Also, FIG. 9D illustrates as a perspective view the LT fuse 3 which is partially fused and removed.
In FIG. 9C, when the LT fuse is removed by the vaporization, a part of the vaporized LT fuse forms a silicon contained dust 31, which scatters onto portions of the interconnection layers 4 on the interlayer insulating film 2, as indicated by an arrow. This causes problems such as short-circuit between interconnections.
Further, the polysilicon layer 3, i.e., LT fuse is formed at the depth t1 of 1 .mu.m or more from the surface of the interlayer insulating film 2. Therefore, after the thick interlayer insulating film 2 over the polysilicon layer 3 is blown off by the pressure increased in accordance with the elevation of the temperature by the laser irradiation, a concave or crater 21 is formed. A larger thickness of the interlayer insulating film 2 over the polysilicon layer 3, i.e., a larger value of t1 will increase the sizes of the crater 21. If the crater 21 reaches the regions for the interconnection layers 4, the interconnection layers 4 are damaged and broken.